The present invention relates to a circuit and a method for controlling an internal voltage, and more particularly, to a circuit and a method for sensing a voltage level of an internal voltage (core voltage) and controlling a release time for the internal voltage using the sensed voltage level in a semiconductor memory device.
A semiconductor memory device receives an external power supply voltage (VDD) lower than a certain value to generate an internal voltage having a voltage level adequate for operations of an internal circuit. A memory device, such as a dynamic random access memory (DRAM), which utilizes a bit line sense amplifier, uses a core voltage (VCORE) to amplify cell data. When a word line is enabled, data in a plurality of memory cells connected to the word line are transferred to bit lines, and then the bit line sense amplifiers sense and amplify voltage difference of bit line pairs.
A voltage level for applying data to bit lines or inversion bit lines by the sense amplifier and charging a capacitor of the cell to store data in the cell in a DRAM is referred to as a core voltage level. A driver for generating the core voltage level is referred to as a core voltage driver. A gradually increased operating speed of the DRAM requires more rapid sensing, and thus the core voltage level of the cell is also required to have ability for more rapid charging.
Accordingly, there is used an overdriving for short-circuiting a core voltage level and an external power supply voltage (VDD) level, which is higher than the core voltage level, according to a current peak for operating the sense amplifier. In addition, there is also used a release driver for discharging the core voltage level in order to prevent the core voltage level from keeping a high voltage level, which is caused by the overdriving, after the overdriving.
Voltages used in the semiconductor memory device are divided to an external power supply voltage and an internal voltage such as a core voltage generated using the external power supply voltage. The internal voltage may be easily varied by internal operations of the semiconductor memory device. Particularly, if there is a possibility that the internal voltage is connected to another voltage having a higher voltage level, or if at least two voltages are connected to the same node, the two voltages may have voltage levels different from set values. This may happen frequently between the external power supply voltage and the core voltage during the operations of the semiconductor memory device.
FIG. 1 is a block diagram of a typical circuit for controlling an internal voltage.
Referring to FIG. 1, a bank controller 10 receives an activation signal RACT having a bank active/precharge information to activate an enable signal SAE1B for performing an overdriving operation on a core voltage and deactivate the enable signal SAE1B when the overdriving operation is finished. Here, the core voltage refers to a voltage generated inside the semiconductor memory device using the external power supply voltage, for use in a core region of the semiconductor memory device.
A release controller 20 receives the enable signal SAE1B deactivated by the bank controller 10 when the over driving operation is finished. Then, the release controller 20 generates a release control signal REL_CTRL for performing a release operation on a core voltage having a voltage level raised by the overdriving operation.
That is, while the enable signal SAE1B is activated to a logic low level, a voltage higher than the core voltage is applied to a core voltage terminal to perform the overdriving operation for raising the voltage level of the core voltage. The overdriving operation is performed for a short time to improve the amplifying speed of the bit line sense amplifier (BLSA).
After the overdriving operation, the core voltage level is higher than a target voltage level. Accordingly, a core voltage release operation is performed to lower the core voltage level to the target voltage level. The core voltage release operation is performed for a predetermined time, e.g., a release time TD1, after the enable signal SAE1B is deactivated to a logic high level, as shown in FIG. 2.
Therefore, while a release control signal REL_CTRL generated by a release controller 30 has a logic high level, the core voltage release driver 30 performs the discharge operation on the core voltage to lower the core voltage level that has been raised to a higher voltage level than the target voltage level by the overdriving operation. In addition, the core voltage active driver 40 is operated during an active period to raise again the core voltage level that has been lowered by the release operation of the core voltage release driver 30. Therefore, while the release control signal REL_CTRL generated by the release controller 30 has a logic high level, the core voltage release driver 30 and the core voltage active driver 40 are operated together to keep the core voltage at the target voltage level.
As described above, in the typical circuit for controlling an internal voltage, the core voltage release driver 30 and the core voltage active driver 40 are operated together for a certain period to keep the core voltage at a target voltage level. That is, while the release control signal REL_CTRL has a logic high level, the core voltage release driver 30 and the core voltage active driver 40 are operated together so that the core voltage level bounces to approach the target voltage level.
In addition, the typical circuit for controlling an internal voltage performs the release operation while the release control signal REL_CTRL has a logic high level. That is, the typical circuit for controlling an internal voltage performs the release operation for a predetermined time, e.g., for a fixed release time TD1 as shown in FIG. 2. Accordingly, even after the core voltage reached the target voltage level, the core voltage release driver 30 continues to operate until the release control signal REL_CTRL goes to a logic low level. That is, there exists a period where the core voltage release driver 30 and the core voltage active driver 40 are operated together unnecessarily, thereby increasing the current consumption. As a result, the typical circuit for controlling an internal voltage fails to consume current efficiently, resulting in an increased current consumption.